1. Field of the Invention
The present invention relates to a frequency synthesizer and, particularly to a frequency synthesizer formed of a phase locked loop (PLL) circuit.
2. Background of the Invention
Frequency synthesizers formed of a PLL circuit generate and output a signal having a frequency of an integral multiple of a reference frequency signal output from a reference oscillator. There have hitherto been developed frequency synthesizers that can change a frequency at an interval smaller than the integral multiple.
FIG. 1 of the accompanying drawings shows an example of such frequency synthesizer. This frequency synthesizer is a fractional-N system and supplies a reference frequency signal output from a reference oscillator 1 to a phase comparator 2.
The phase comparator 2 detects a phase difference between a frequency-divided signal output from a frequency divider 7, which will be described later on, and the reference frequency signal. The phase comparator 2 supplies an error signal based on the detected phase difference to an adder 3. The adder 3 adds an interpolation signal output from an automatic phase interpolating circuit 9, which will be described later on, to the error signal supplied thereto from the phase comparator 2. The adder 3 supplies a resulting added error signal to a low-pass filter (LPF) 4. The LPF 4 converts the error signal to a DC error signal. The LPF 4 supplies a resulting DC error signal to a voltage-controlled oscillator (VCO) 5 as a control signal. The VCO 5 supplies an oscillation signal to a frequency signal output terminal 6, the frequency divider 7 and a control unit 8.
The frequency divider 7 divides the oscillation output from the VCO 5. The frequency divider 7 alternately switches a frequency-dividing ratio to a predetermined value 1/N (N is an integer) or 1/(N+1) under the control of the control unit 8. The frequency divider 7 supplies a frequency-divided signal to the phase comparator 2. The control unit 8 controls the automatic phase interpolating circuit 9 such that the automatic phase interpolating circuit 9 outputs an interpolation signal at every predetermined period.
An operation of the frequency synthesizer will be described with reference to timing charts of FIGS. 2A to 2C. Assuming that the reference oscillator 1 outputs a reference frequency signal of a period shown in FIG. 2A, then the frequency divider 7 has a frequency-dividing ratio of 1/N at a certain timing t.sub.a of the reference frequency signal as shown in FIG. 2B. The frequency divider 7 changes the frequency-dividing ratio of 1/N to 1/(N+1) when the reference frequency signal is advanced from the timing t.sub.a to a timing t.sub.b. Further, the frequency divider 7 resets the frequency-dividing ratio of 1/(N+1) to 1/N when the reference frequency signal is advanced from the timing t.sub.b to a timing t.sub.c. Therefore, the frequency divider 7 repeats the switching of the frequency-dividing ratios of 1(N+1) and 1/N at every period.
When the frequency-dividing ratios are set as described above, the phase comparator 2 detects a predetermined phase error .phi..sub.1 at a timing point where the frequency-dividing ratio is switched from 1/N to 1/(N+1) at every two periods of the reference frequency signal as shown in FIG. 2C. As a consequence, the oscillation frequency of the VCO 5 is disturbed.
In the frequency synthesizer shown in FIG. 1, the automatic phase interpolating circuit 9 outputs an interpolation signal for interpolating the phase error .phi..sub.1 at every two periods of the reference frequency signal. Then, the adder 3 adds the interpolation signal to the phase error signal to cancel the phase error .phi..sub.1 out so that the VCO 5 outputs a stable oscillation output.
Therefore, the VCO 5 can output a frequency signal having a frequency (N+0.5) times the frequency of the reference frequency signal. Thus, the frequency synthesizer can change the frequency at an interval smaller than the integral multiple.
In the case of the frequency synthesizer shown in FIG. 1, however, the automatic phase interpolating circuit 9 and peripheral circuits become complicated in arrangement. Specifically, the automatic phase interpolating circuit 9 is formed as a digital-to-analog (D/A) converter for converting digital control data to data of analog level. Thus, the arrangement of the automatic phase interpolating circuit 9 is complicated. Therefore, if the frequency synthesizer includes the automatic phase interpolating circuit, then the PLL circuit becomes complex in arrangement.